Reliable Semiconductor IP Solutions
for Modern ASIC Design

Accelerate your digital design with rigorously engineered interface IP cores — each listed with its current verification status.

Accelerate Your Silicon Success with High-Quality IP

At RiRe Technologies, we are dedicated to providing a highly focused and comprehensive spectrum of premium interface and connectivity IP cores, meticulously engineered to meet the demanding constraints of modern ASIC and SoC architectures. We understand that today’s complex semiconductor landscape requires components that go beyond basic functionality. That is why our advanced communication protocols and interconnect subsystems are purpose-built from the ground up for absolute reliability, maximum data throughput, and optimized power-performance-area (PPA) metrics. 

By prioritizing robust design methodologies, we ensure our IP solutions deliver seamless, flawless integration into your existing digital environment—ultimately helping your engineering teams reduce silicon risks, lower integration costs, and significantly accelerate your product’s time-to-market.

Advanced Connectivity Subsystems

I3C Host IP Subsystem with Proprietary Features

  • Supports only Primary Controller Mode, does not support Secondary Controller or standalone Target Mode
  • Designed for compliance with MIPI I3C Basic v1.2, HCI v1.2, and TCRI v1.0 specifications.
  • Equipped with essential capabilities like Dynamic Address Assignment (DAA), In-Band Interrupts (IBI), and Hot Join support.
  • Backward compatible with the I2C target IP devices per I3C specification
  • 32-bit AMBA AXI4-Lite Slave Interface to an application processor
  • 32-bit AXI4 Master Interface for DMA Mode
  • Status: In development — engineering evaluation access under NDA.
Explore

Peripheral Interface IPs

I2C Master IP

Explore
  • AMBA APB4 compliance (backward compatible with APB3) ensures seamless, drop-in integration into modern ASIC architectures.
  • Standard I2C specification compatibility supports Standard-mode (100 kbps), Fast-mode (400 kbps), and Fast-mode Plus (1 Mbps).
  • Integrated glitch filter and watchdog timer hardware blocks provide robust noise suppression and autonomous system recovery.
  • Verification signed off with complete documentation set; synthesised and validated on FPGA platforms.
  • Status: Verification signed off. Documentation set — datasheet, integration guide, verification signoff report — available for evaluation under NDA.

SMBus Master IP

  • AMBA APB4 compliance (backward compatible with APB3) ensures seamless, drop-in integration into modern System-on-Chip (SoC) architectures.
  • SMBus 3.0 protocol compatibility provides full compliance with standard System Management Bus specifications and legacy power management chips.
  • Packet Error Checking (PEC) support includes built-in hardware CRC-8 generation and checking to ensure robust packet data integrity.
  • Verification signed off with complete documentation set.
  • Status: Verification signed off. Documentation set — datasheet, integration guide, verification signoff report — available for evaluation under NDA.
Explore

UART Controller IP

  • AMBA APB4 compliance (backward compatible with APB3) ensures seamless, drop-in integration into modern SoC architectures.
  • Backward compatible with industry-standard NS16550A software drivers.
  • Configurable register interface supporting both 8-bit and 32-bit data bus widths.
  • Status: In final verification — release 3rd quarter.
Explore

SPI Master IP

  • AMBA APB4 compliance (backward compatible with APB3) ensures seamless, drop-in integration into modern System-on-Chip (SoC) architectures.
  • Fully compatible with standard 3-pin and 4-pin Motorola SPI interfaces and legacy devices.
  • Supports flexible, user-defined character lengths (2 to 16 bits) to interface with diverse peripheral components.
  • Status: In definition — planned .
Explore