I3C Host IP Subsystem

Overview

Our I3C Host IP Subsystem is designed for compliance with MIPI I3C Basic v1.2, MIPI I3C HCI v1.2, and MIPI I3C TCRI v1.0 specifications, and is under active development. Purpose-built exclusively as a dedicated I3C Primary Controller, this subsystem completely eliminates the massive silicon overhead and routing complexity associated with generic multi-mode or target-capable IP blocks. The result is an ultra-lean, area-optimized core that drastically minimizes gate count and static power leakage while delivering robust SDR data transfers of up to 12.5 Mbps.

The architecture features comprehensive In-Band Interrupt (IBI) support, advanced asynchronous timing controls, and an integrated master descriptor ring architecture for high-performance DMA operations. It provides backward compatibility with legacy Fast-mode (Fm) and Fast-mode Plus (Fm+) I2C devices, and and is designed to support the JEDEC JESD403-1 specification.

Core Features

  • Area-Optimized Host Architecture: Pure Primary Controller design that strips away unused secondary controller and target logic to minimize silicon area, optimize routing, and reduce static power leakage.

  • High-Efficiency Data Rates: Full SDR mode support driving data transfers up to 12.5 Mbps.

  • Automated Bus Provisioning: Built-in hardware acceleration for Dynamic Address Assignment (DAA) and Common Command Code (CCC) execution.

  • Advanced Target Handling: Seamless integration of In-Band Interrupts (IBI) and Hot Join support for dynamic peripheral insertion.

  • Native AMBA Bus Interfaces: High-bandwidth system integration via an on-chip 32-bit AMBA AXI4-Lite Slave interface for host register access and a 32-bit AXI4 Master interface for dedicated DMA operations.

  • DDR5 Sideband Channel Ready: Designed to support the JEDEC JESD403-1 specification for next-generation computing platforms.

  • Legacy Interoperability: Backward compatible with standard Fast-mode (Fm) and Fast-mode Plus (Fm+) I2C target devices.

  • Robust Fault Tolerance: Hardware-level error detection and autonomous bus recovery protocols, complemented by an integrated Digital Noise Filter (DNF) on SCL and SDA inputs.

  • Flexible Transaction Blocks: Handles up to 255 continuous write or read bytes within a single command, alongside a low-power hardware Wake Up function.

  • Configurable Features
         – TX and RX FIFO (Depth of up to 512 locations)
         – Command Queue Depth
         – Response Queue Depth
         – DMA Rings (Up to 8 Command/Response descriptor rings)
         – Frequency Divider for SCL via Configuration registers

Status: In development (RTL and verification). Engineering evaluation and early-access engagement available under NDA.

Block Diagram

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